The present invention relates generally to the design of flip-chip packages used in the manufacture of integrated circuits. More specifically, but without limitation thereto, the present invention relates to testing for electromigration in a flip-chip ball grid array package.
An important issue in microelectronic packaging is reliability. Technologies for microelectronic packaging are developed not only to manufacture microelectronic packages at low cost, but also to ensure that the performance of the microelectronic packages will not deteriorate over their service life. A significant cause of such deterioration problem is electromigration in the interconnects of flip-chip ball grid array (FPBGA) packages. Parameters that influence the mean time to failure (MTTF) of an FPBGA package are material properties, temperature, current density and the physical dimensions, which affect the current density. Accordingly, a need exists for an apparatus and/or method for extending the service life of microelectronic packages.
In one aspect of the present invention, a package for a flip-chip ball grid array includes a die having a plurality of I/O pads formed on a metal layer, a plurality of traces formed on the die electrically connecting adjacent pairs of the I/O pads, a plurality of bumped interconnects formed on the I/O pads, and a substrate having a plurality of bump-to-bump interconnects formed on a top surface of the substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.
In another aspect of the present invention, a method of making a package for a flip-chip ball grid array includes providing a die having a plurality of I/O pads, forming a plurality of traces on the die electrically connecting adjacent pairs of the I/O pads, forming a plurality of bumped interconnects on the I/O pads, and forming a plurality of bump-to-bump interconnects on a top surface of a substrate adjacent to the die wherein the plurality of bump-to-bump interconnects is electrically coupled to the plurality of bumped interconnects so that the plurality of bumped interconnects is connected in series.